FIG. 1 of the accompanying drawings illustrates a typical active matrix display, for example of the liquid crystal type, comprising an active matrix 1 of N rows and M columns of picture elements (pixels). The columns are connected to M column electrodes which are connected to a data line driver 2 including an M-phase clock generator. The rows are connected to N row electrodes which are connected to a scan line driver 3 including an N-phase clock generator. In a typical display of this type, the M-phase clock generator is required to produce clock pulses at the data rate so as to sample incoming data for refreshing the active matrix 1 a row at a time. The N-phase clock generator is required to produce pulses at a scan rate so as to drive the scan lines one at a time for refreshing the active matrix 1 row by row.
Normal operation of a display of this type is such that the data are sampled to the data lines from left to right and the scan lines are driven from the top to the bottom of the active matrix 1. It is desirable to reduce or minimise the area occupied by the drivers 2 and 3. For example, when these drivers are integrated on the display substrate of a panel display, this allows a smaller bezel size to be used for the panel. Alternatively or additionally, this allows the integration of additional circuits without having to increase the panel size.
In some applications, it is desirable to be able to reverse the order of data and/or scan pulses such that the data are sampled to the data lines from right to left and/or such that the scan lines are driven from the bottom to the top of the active matrix 1. For example, this allows an image to be inverted, reflected or rotated without the need for extra memory in a data buffer supplying image data to the display and without the risk of image distortion. A common application of such an arrangement is to allow rotation of a display panel after manufacture to give a better fit in a host device.
A known type of multi-phase clock generator suitable for use in the drivers 2 and 3 of FIG. 1 comprises a shift register in the form of cascaded D-type flip-flops. The shift register is controlled by a clock so as to pass a single stored logic state along the chain of flip-flops. For example, FIG. 2 illustrates an example of the waveforms appearing at five outputs OUT1 to OUT5 of such a shift register. The five phase clock pulses appear in sequence on the outputs and do not overlap with each other. FIG. 3 of the accompanying drawings illustrates an alternative arrangement in which there is an overlap between consecutive pairs of clock pulses.
FIG. 4 of the accompanying drawing illustrates another type of shift register suitable for such an application and disclosed in GB2 345 207. In this simplified example, the shift register comprises five stages with each stage comprising a reset-set flip-flop (11–15) and a gate circuit (16–20), which receives complementary clock pulses CK and CKB. Each gate circuit has complementary inputs G and GB for receiving complementary outputs Q and QB from the flip-flop (RSFF) of the same stage and has complementary clock inputs CK and CKB. In the first, third and fifth stages, the gate clock inputs CK and CKB receive the clock signals CK and CKB, respectively, whereas, in the second and fourth stages, the clock inputs CK and CKB receive the clock signals CKB and CK, respectively.
In the intermediate stages of the shift register, the output O of the gate circuit comprises the output of the shift register and is also supplied to the re-set input R of the flip-flop of the preceding stage and to the set input S of the flip-flop of the succeeding stage. When enabled, the gate circuits 16, 18, 20 of the first, third and fifth stages supply a high state to their outputs O in response to a rising edge of the clock signal CK whereas the gate circuits 17 and 19 of the second and fourth stages respond to a falling edge of the clock signal CK.
During operation, for example when the flip-flop 12 of the second stage is set, its direct or non-inverting output Q is at a logic high level whereas its inverted or complementary output QB is at a logic low level so that the gate circuit 17 is enabled. In response to the arrival of the next falling edge of the clock signal CK the gate circuit 2 passes a high state to its output (O), which sets the flip-flop 13 and re-sets the flip-flop 11. The flip-flop 13 enables the gate circuit 18 which in turn sets the flip-flop 14 and re-sets the flip-flop 12 at the next rising edge of the clock signal CK.
The output signals produced by the shift register shown in FIG. 4 form a multi-phase clock with overlapping between consecutive output pulses. Depending on the application of the shift register, this overlapping may be exploited or removed.
A shift register of this type may be made bi-directional by controlling the direction of passage of the set and re-set signals, for example using transmission gates. However, this requires extra transistors and an up/down control line extending along the length of the shift register.
U.S. Pat. No. 5,410,583, U.S. Pat. No. 6,339,631 and U.S. Pat. No. 6,345,085 disclose an alternative arrangement in which an input multi-phase clock signal is supplied to a shift register arrangement with each stage passing one of the clock signals to its output. Each stage is enabled by the output of the preceding stage and is disabled by another of the clocks. Such arrangements are relatively compact but rely on nMOS pass transistors which, depending on the integration technology used, may have to be replaced with complementary transmission gates, thus increasing the size of such a shift register. No technique for providing bi-directional operation is disclosed.
U.S. Pat. No. 5,859,630 discloses a similar type of arrangement which is capable of bi-directional operation. The order in which clock pulses appear on the multi-phase clock inputs determines the shifting direction of the shift register. Although this technique does not require transmission gates for controlling the direction of shifting, each stage is more complex in that it requires two parallel control circuits controlling a single transistor to pass a signal. Also, each stage is required to be connected to the preceding two stages and the succeeding two stages so that extra connections are required.
The term “reset-over-set flip-flop circuit” as used herein is defined to mean any circuit which operates as a flip-flop in which resetting has priority over setting. Thus, when an active reset signal is present at a reset input, the flip-flop is or remains reset irrespective of the state of a signal at a set input. When an active setting signal is received at the set input, the flip-flop is only set in the absence of an active reset signal at the reset input (which is equivalent to an inactive reset signal at the reset input).